LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY FnDecoder_tb IS
END FnDecoder_tb;

ARCHITECTURE archFnDecoder_tb OF FnDecoder_tb IS

	COMPONENT FnDecoder IS
		PORT (
			UCP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
			F0 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
			F1 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0));
	END COMPONENT;

	SIGNAL UCP, F0, F1 : STD_LOGIC_VECTOR(1 DOWNTO 0);

BEGIN
	UUT : FnDecoder PORT MAP(UCP, F0, F1);
	sim_proc : PROCESS
	BEGIN
		UCP <= "00";
		WAIT FOR 100 ns;

		UCP <= "01";
		WAIT FOR 100 ns;

		UCP <= "10";
		WAIT FOR 100 ns;

		UCP <= "11";
		WAIT FOR 100 ns;
		WAIT;
	END PROCESS;
END archFnDecoder_tb;